The present invention relates to electronic devices, and more particularly, to analog to digital converters (ADCs).
In certain electronic devices, ADCs are used for converting an analog signal into a digital format having one or more bits. Examples of such electronic devices include, but are not limited to, imaging, communication, and display devices. As can be expected, the ADC is a fundamental component of these electronic devices. Referring to the examples above, the ADC typically receives analog signals from a signal source (e.g., an antenna, a sensor, or a transducer), which is then converted by the ADC to a digital code representing the data.
An analog-to-digital converter (ADC) can use one of several architectures, such as a flash architecture, a delta-sigma architecture, and a pipelined architecture. Among the ADC architectures, the pipelined architecture is widely used in applications, such as video imaging systems, digital subscriber loops, Ethernet transceivers, and wireless communications. The pipelined ADC is also known as a sub-ranging ADC.
Some ADCs may include latch (or comparator) circuits as decision elements. When using multiple latches, it is necessary to have an indication of when the conversion is complete. As the number of latches in the ADC increases, additional logic is needed to generate a signal indicating that the analog to digital conversion has been completed. For example, a 4-bit flash ADC would require fifteen input gates, such as AND gates, to provide such an indication.
Another known architecture is the successive approximation register (SAR) ADC. A SAR ADC samples an input voltage and compares it to a plurality of threshold voltages on a bit-by-bit basis. When converting an analog voltage to a multi-bit digital codeword, a SAR ADC will perform one decision for each bit in the codeword. To this end, the SAR ADC often includes one or more capacitor arrays to store sampled voltages and to generate reference voltages and a comparator to compare the sampled voltage to each reference voltage and perform bit decisions. However, iterative operation of the SAR ADC limits the maximum conversion rate of the SAR ADC.
To maximize a conversion rate of an ADC, it may be necessary to ensure that components of the ADC will be utilized at the highest rates possible. Any time spent while ADC components are idle can lower the ADC's conversion rate. To this end, the inventor has identified a need in the art for an ADC that can determine when a first component of the ADC has completed an operation so that a subsequent component may commence operation.